Memory Bandwith Based Performance Tuning Prediction Memory-bandwidth Based Performance Tuning and Prediction

It is the contention of this paper that memory bandwidth has become the single most important determinant of performance on modern computer systems built from commodity processors. This contention is supported by a study of several representative scientiic programs executed on the Silicon Graphics Origin2000, in which memory bandwidth is far more critical to performance than CPU speed or bandwidths between diierent levels of cache. This result leads us to conjecture that measuring and predicting data transfer time between memory and cache could be an eeective way to predict and tune program performance. We present the design of a performance tool based on this idea. This tool could use bandwidth analysis to predict program performance and locate memory hierarchy performance problems within an application. The eeectiveness of such a tool was demonstrated on the NAS SP benchmark. In the tuning step, this approach identiied three loop nests with low memory hierarchy performance that could be modiied through simple transformations to achieve a 19% overall performance improvement. We hand-applied the static estimation method to two subroutines and found that the diierence between the estimated capacity misses and the actual number of cache misses is less than 3%. Given accurate static estimation, this approach can predict SP running time with an error of less than 10%.